1. Field of the Invention
The present invention relates to a flat panel display and a method of manufacturing the same. More particularly, the present invention relates to an organic electroluminescence (EL) display and a method of manufacturing the same.
2. Description of the Related Art
Electroluminescence (EL) displays have recently attracted considerable attention as a flat panel display. The EL displays generally use a thin film transistor (TFT) as a switching element.
FIG. 1 is a cross-sectional view illustrating a conventional EL display. The conventional EL display of FIG. 1 is manufactured as follows. First, a first insulating layer 11 is formed on the whole surface of a transparent insulating substrate 10. The first insulating layer 11 serves as a buffer layer. The transparent insulating substrate 10 is made of a glass or a synthetic resin. A polysilicon layer is deposited on the buffer layer 11 and patterned into a semiconductor layer 13 using a first mask.
A second insulating layer 15 is formed over the whole surface of the transparent insulating substrate 10 and covers the semiconductor layer 13. The second insulating layer 15 serves as a gate insulating layer.
A first metal layer is deposited on the first insulating layer 15 and patterned into a gate electrode 16 and a first capacitor electrode 17 using a second mask.
An n-type or a p-type impurity is ion-doped into the semiconductor layer 13 to form source and drain regions 13-1 and 13-2. A portion 13-3 of the semiconductor layer 13 under the gate electrode 16 serves as an active area.
A third insulating layer 19 is formed over the whole surface of the transparent insulating substrate 10 and covers the gate electrode 16 and the first capacitor electrode 17. The insulating layer 19 serves as an inter-insulating layer.
Subsequently, the second and third insulating layers 15 and 19 are etched using a third mask to form first and second contact holes 20-1 and 20-2. The first contact hole 20-1 exposes a portion of the source region 13-1, and the second contact hole 20-2 exposes a portion of the drain region 13-2.
A second metal layer is deposited over the whole surface of substrate and patterned into source and drain electrodes 22-1 and 22-2 and a second capacitor electrode 22-3 using a fourth mask. The source electrode 22-1 contacts the source region 13-1 through the first contact hole 20-1, and the drain electrode 22-2 contacts the drain region 13-2 through the second contact hole 20-2. The second capacitor electrode 22-3 extends from either of the source and drain electrodes 22-1 and 22-2, for example the source electrode 22-1. Consequently, a TFT 51 and a capacitor 52 of the conventional EL display are completed.
At this point, a portion of the third insulating layer 19 between the first and second capacitor electrodes 17 and 22-3 serves as a dielectric layer of the capacitor 52.
Thereafter, a fourth insulating layer 25 is formed over the whole surface of the transparent insulating substrate 10. The fourth insulating layer 25 serves as a passivation layer. The passivation layer 25 is etched to form a via hole 26 at a region corresponding a portion of either of the source and drain electrodes 22-1 and 22-2 using a fifth mask. In FIG. 1, the via hole 26 exposes a portion of the drain electrode 22-2.
A transparent material layer is deposited on the passivation layer 25 and patterned into a pixel electrode 27 using a sixth mask. The pixel electrode 27 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrode 27 electrically contacts the drain electrode 22-2 through the via hole 26. The pixel electrode 27 is used as an anode electrode.
A fifth insulating layer 28 is formed over the whole surface of the transparent insulating substrate 10. The fifth insulating layer 28 serves as a planarization layer. The planarization layer 28 is etched using a seventh mask to form an opening portion 28-1. The opening portion 28-1 exposes a portion of the anode electrode 27.
An organic EL layer 29 is formed on the exposed portion of the anode electrode 27 and the planarization layer 28. A third metal layer, i.e., a cathode electrode 30 is deposited to cover the whole display area, completing the conventional organic EL display 53.
However, the conventional organic EL display has the following disadvantages. Since seven complicated mask processes are used to manufacture the organic EL display, production cost is high and manufacturing yield is low. Also, during an etching process to form the anode electrode 27, an etching solution can soak into the source and drain electrodes 22-1 and 22-2, whereupon the source and drain electrodes 22-1 and 22-2 can be damaged, thereby deteriorating electrical characteristics of the TFT. Furthermore, light emitted from the organic EL layer 29 is reflected from an interface between the gate insulating layer 15 and the inter-insulating layer 19, and an interface between the inter-insulating layer 19 and the passivation layer 25, thereby lowering a light transmittance.